NCP1083DEG【PDF 15/18 页】IC CONV CTLR POE-PD 40W 20-TSSOP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录45

11页 12页 13页 14页 [15页]16页 17页 18页

NCP1083

http://onsemi.com

When VPORT reaches the UVLO_on level, the Cpd

capacitor is charged with the INRUSH current (in order to

limit the internal power dissipation of the passswitch).

Once the Cpd capacitor is fully charged, the current limit

switches from the inrush current to the current level (ilim1)

as shown in Figure 15. This transition occurs when both

following conditions are satisfied:

1. The VDS of the passswitch is below the

Vds_pgood low level (1 V typical).

2. The passswitch is no longer in current limit

mode, meaning the gate of the passswitch is

high (above 2 V typical).

The operational current limit will stay selected as long as

Vds_pgood is true (meaning that RTNVPORTN

1,2

below the high level of Vds_pgood). This mechanism allows

a current level transition without any current spike in the

passswitch because the operational current limit (ilim1) is

enabled once the passswitch is not limiting the current

anymore, meaning that the Cpd capacitor is fully charged.

Thermal Shutdown

The NCP1083 includes thermal protection which shuts

down the device in case of high power dissipation. Once the

thermal shutdown (TSD) threshold is exceeded, following

blocks are turned off:

" DCDC controller

" Passswitch

" VDDH and VDDL regulators

" CLASS regulator

When the TSD error disappears and if the input line

voltage is still above the UVLO level, the NCP1083

automatically restarts with the current limit set in the inrush

state, the DCDC controller is disabled and the Css

(softstart capacitor) discharged. The DCDC controller

becomes operational as soon as capacitor Cpd is fully

charged.

DCDC Converter Controller

The NCP1083 implements a current mode DCDC

converter controller which is illustrated in Figure 16.

VDDL

360 mV

Oscillator

COMP

Gate

Driver

PWM comp

OSC

VDDL

Blanking

time

Current Slope

Compensation

Softstart

1.45 V

1.2 V

Current limit

comp

9 V LDO

3.3 V LDO

GATE

VDDH

ARTN

VPORTP

Set

CLK

Reset

CLK

Figure 16. DCDC Controller Block Diagram

5 kW

10 mA

11 kW

5 mA

Sawtooth

Generator

Internal VDDH and VDDL Regulators and Gate Driver

An internal linear regulator steps down the VPORTP

voltage to a 9 V output on the VDDH pin. VDDH supplies

the internal gate driver circuit which drives the GATE pin

and the gate of the external power MOSFET. The NCP1083

gate driver supports an external MOSFET with high Vth and

high input gate capacitance. A second LDO regulator steps

down the VDDH voltage to a 3.3 V output on VDDL. VDDL

powers the analog circuitry of the DC-DC controller and

nCLASS_AT blocks. Moreover it can provide current to

light a LED connected on the nCLASS_AT pin.

In order to prevent uncontrolled operations, both regulators

include poweronreset (POR) detectors which prevent the

DCDC controller from operating when either VDDH or

VDDL is too low. In addition, an overvoltage lockout

(OVLO) on the VDDH supply disables the gate driver in case

of an openloop converter with a configuration using the bias

winding of the transformer (see Figure 4).

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式